1. Field of this Invention
This disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having an internal supply voltage driver to provide internal supply voltage.
As the integration density of semiconductor memory devices increases and the high power up speed is required, the structure of internal supply voltage generating means of a memory cell array is very important especially in hand-held systems. Namely, when the internal supply voltage rises with the external supply voltage, the internal supply voltage reaches a level where the memory device can operate in a stabilized state after the external supply voltage reaches the appropriate level. This difference in rising time of the voltage level causes various problems.
For example, when a system accesses the semiconductor memory device, if the system accesses the memory device only according to the external supply voltage level, there is a possibility that the system uses the internal supply voltage that has not yet reached the minimum voltage level for operating the memory device. It means that the semiconductor memory device will incur errors.
2. Description of Prior Art
FIG. 1 is a block diagram of the conventional memory device. In this figure, the memory device will be considered as a flash memory device.
The memory device comprises an internal circuit 60, an Internal Voltage Converter (IVC) 500, a standby IVC driver 200, a power level detector 120, a CE buffer 140 and a CMD buffer 160. During the power-up period, the power level detector 120 generates a signal PDT with the external supply voltage. The signal PDT inputs to the internal circuits 60 and the CMD register 160 to reset the level in the memory device. The standby IVC driver 200 converts the external supply voltage to the internal supply voltage according to the level of reference voltage Vref. The standby IVC driver 200 always provides the internal voltage to the internal circuits after power up.
In FIG. 1, the IVC 500 comprises an active IVC controller and an active IVC driver. The active IVC controller (550 in FIG. 3) is activated only when CE buffer 140 and CMD register 160 generate an enable and busy signal, respectively. Those of skill in the art will appreciate that a standby IVC driver 200 is used in the standby mode for reducing the power consumption and the active IVC driver (550) is used during periods of active device operation to supply a sufficiently high voltage quickly to the memory device even when power consumption is high.
The circuit depicted in FIG. 2 is generally used in standby IVC driver 200. In FIG. 2, during power up, the standby IVC driver 200 receives a reference voltage Vref and an external supply voltage Vext to generate the internal voltage Vint. In the standby IVC driver, no signals are input to the driver 200 except the reference voltage Vref. Vref itself does not comprise other signals. Vref is controlled only by external voltage Vext. Because the standby IVC driver 200 always operates during the period of active device operation, driver 200 must generate an internal supply voltage Vint according to the level of reference voltage Vref. During that time, the power-up slopes of Vext and Vint are different from one another, as shown in FIG. 4. If the internal supply voltage is supplied to the memory device according to the external supply voltage, whereby Vext goes to the saturational level Vext at t1, the internal supply voltage remains lower than the minimum operating voltage Vdet over the time range A. As a consequence, an error may occur in the memory device.
Generally, the rise time of Vint for providing minimum operating voltage Vdet has taken approximately 6 xcexcs. But recently, especially in hand-held systems, the IVC driver 200 is required to provide the internal supply voltage Vint to the memory device within 1 xcexcs. As shown FIG. 3, because there is no power-up signal input to the active IVC controller 550, the internal voltage in accordance with the prior art is provided only by the standby IVC driver during the power-up period.
Accordingly, present invention provides an internal supply voltage far more quickly than the prior art.